Bootstrapping 4

Test of patched GHC 6.10.1 produced the following:

Unexpected failures:

 1861(normal,optc,hpc,threaded1,threaded2)
 1914(ghci)
 2594(normal,optc,hpc,threaded1,threaded2)
 andy_cherry(hpc)
 arith011(optc,hpc,threaded2)
 barton-mangler-bug(normal,optc,hpc,threaded1,threaded2)
 break024(ghci)
 cabal01(normal)
 conc042(threaded2)
 conc043(threaded2)
 conc044(threaded2)
 conc045(threaded2)
 concprog001(hpc)
 driver062.1(normal)
 driver062.2(normal)
 driver062.3(normal)
 driver062.4(normal)
 driver062.5(normal)
 driver081.1(normal)
 driver081.2(normal)
 dynamic_flags_001(normal)
 enum01(optc,hpc,threaded2)
 enum02(optc,hpc,threaded2)
 enum03(optc,hpc,threaded2)
 ffi019(normal,optc,hpc,ghci,threaded1,threaded2)
 gadt23(normal)
 ghciprog004(normal)
 hClose002(normal,optc,hpc,ghci,threaded1,threaded2)
 hpc_raytrace(normal,optc,hpc,threaded1,threaded2)
 joao-circular(normal,optc,hpc,threaded1,threaded2)
 num012(normal,optc,hpc,ghci,threaded1,threaded2)
 process007(normal,optc,hpc,ghci,threaded1,threaded2)
 random1283(threaded2)
 recomp001(normal)
 recomp004(normal)
 seward-space-leak(ghci)
 tcrun007(normal,optc,hpc,ghci,threaded1,threaded2)
 testblockalloc(normal,threaded1)
 user001(normal,optc,hpc,ghci,threaded1,threaded2)

When building the ghc-HEAD-native with the native code generator turned on, looks like the genSwitch function for SPARC is missing from MachCodeGen.hs. Also missing are the ALLOCATABLE_REGS defs from MachRegs.lhs.

Went through the description of the register set in includes/MachRegs.h. Looks like there are 3 allocatable integer regs, 6 allocatable double regs, and 4 allocatable float regs. The graph coloring allocator currently only allocates doubles, not single precision floats as well. Will have to come back and check this.

isRegRegMove and mkRegRegMovInstr from RegAllocInfo.hs were missing. So was regDotColor from RegAllocStats.hs, isFloatSize from MachRegs.lhs

MachRegs.lhs has a function mkVReg which determines the vreg to use for a particular size word. This is the source of single precision floating point vregs. All the word size code has also rotted. The sparc Size type is different from the ones use for the i386(64) and ppc. Should come back and fix this, but for now I've just added the missing functions and kept the old size type.

In MachInstrs.hs i386 has OpReg but sparc has RI, similar. Should refactor sparc code to use OpReg.